Digital Design/Verification Intern

Semifront is looking for folks who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad-level Microarchitecture and Architecture Specs. Skills and other requirements: 1. Excellent/good Verilog/SystemVerilog/Perl Skillset 2. The coding will be Perl mixed Verilog/SV 3. Knowledge of Make, Python, Bash is an advantage, but not mandatory 4. The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory 5. The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to detail and humility to learn from the right feedback Who can apply: 1. Fresher/junior engineers looking for an opportunity. 2. People looking for training/upscaling in the domain can apply. 3. People looking to explore in-depth from scratch ASIC design can also apply. Additional information: 1. Opportunity to work in complex ASIC product design from scratch 2. Opportunity to learn alongside experienced and passionate engineers who have helped build IPs/SoCs from scratch 3. Monthly stipend/remuneration 4. Facility to work partially remotely for excellent individuals 5. Opportunity to convert to full-time engineers for excellent performing individuals.